? 2005 fairchild semiconductor corporation ds009954 www.fairchildsemi.com november 1988 revised march 2005 74ac273 ? 74act273 octal d-type flip-flop 74ac273 74act273 octal d-type flip-flop general description the ac273 and act273 have eight edge-triggered d-type flip-flops with individual d-type inputs and q outputs. the common buffered clock (cp) and master reset (mr ) input load and reset (clear) all flip-flops simultaneously. the register is fully edge-triggered. the state of each d- type input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop?s q output. all outputs will be forced low independently of clock or data inputs by a low voltage level on the mr input. the device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. features ideal buffer for microprocessor or memory eight edge-triggered d-type flip-flops buffered common clock buffered, asynchronous master reset see 377 for clock enable version see 373 for transparent latch version see 374 for 3-state version outputs source/sink 24 ma 74act273 has ttl-compatible inputs ordering code: device also available in tape and reel. specify by appending suffix letter ? x ? to the ordering code. pb-free package per jedec j-std-020b. note 1: ? _nl ? indicates pb-free package (per jedec j-std-020b). device available in tape and reel only. fact is a trademark of fairchild semiconductor corporation. order number package package description number 74ac273sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74ac273sj m20d pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac273mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac273pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74act273sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74act273sj m20d pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74act273mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act273mtcx_nl (note 1) mtc20 pb-free 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act273pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 74ac273 74act273 connection diagram logic symbols ieee/iec pin descriptions mode select-function table h high voltage level l low voltage level x immaterial low-to-high transition logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. pin names description d 0 ? d 7 data inputs mr master reset cp clock pulse input q 0 ? q 7 data outputs operating mode inputs outputs mr cp d n q n reset (clear) l x x l load ? 1' h hh load ? 0' h ll
3 www.fairchildsemi.com 74ac273 74act273 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact circuits outside databook specifications. dc electrical characteristics for ac note 3: all outputs loaded; thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . supply voltage (v cc ) 0.5v to 7.0v dc input diode current (i ik ) v i 0.5v 20 ma v i v cc 0.5v 20 ma dc input voltage (v i ) 0.5v to v cc 0.5v dc output diode current (i ok ) v o 0.5v 20 ma v o v cc 0.5v 20 ma dc output voltage (v o ) 0.5v to v cc 0.5v dc output source or sink current (i o ) r 50 ma dc v cc or ground current per output pin (i cc or i gnd ) r 50 ma storage temperature (t stg ) 65 q c to 150 q c junction temperature (t j ) (pdip) 140 q c supply voltage (v cc ) ac 2.0v to 6.0v act 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) 40 q c to 85 q c minimum input edge rate ( ' v/ ' t) ac devices v in from 30% to 70% of v cc v cc @ 3.3v, 4.5v, 5.5v for ac 125 mv/ns minimum input edge rate ( ' v/ ' t) act devices v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v for act 125 mv/ns symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out 0.1v input voltage 4.5 2.25 3.15 3.15 v or v cc 0.1v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out 0.1v input voltage 4.5 2.25 1.35 1.35 v or v cc 0.1v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 output voltage 4.5 4.49 4.4 4.4 v i out 50 p a 5.5 5.49 5.4 5.4 v in v il or v ih 3.0 2.56 2.46 i oh 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma (note 3) v ol maximum low level 3.0 0.002 0.1 0.1 output voltage 4.5 0.001 0.1 0.1 v i out 50 p a 5.5 0.001 0.1 0.1 v in v il or v ih 3.0 0.36 0.44 i ol 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 3) i in maximum input 5.5 r 0.1 r 1.0 p av i v cc , gnd (note 5) leakage current i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 4) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 4.0 40.0 p av in v cc (note 5) supply current or gnd
www.fairchildsemi.com 4 74ac273 74act273 ac electrical characteristics for ac note 6: voltage range 3.3 is 3.3v r 0.3v voltage range 5.0 is 5.0v r 0.5v ac operating requirements for ac note 7: voltage range 3.3 is 3.3v r 0.3v voltage range 5.0 is 5.0v r 0.5v v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 6) min typ max min max f max maximum clock 3.3 90 125 75 mhz frequency 5.0 140 175 125 t plh propagation delay 3.3 4.0 7.0 12.5 3.0 14.0 ns clock to output 5.0 3.0 5.5 9.0 2.5 10.0 t phl propagation delay 3.3 4.0 7.0 13.0 3.5 14.5 ns clock to output 5.0 3.0 5.0 10.0 2.5 11.0 t phl propagation delay 3.3 4.0 7.0 13.0 3.5 14.0 ns mr to output 5.0 3.0 5.0 10.0 2.5 10.5 v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 7) typ guaranteed minimum t s setup time, high or low 3.3 3.5 5.5 6.0 ns data to cp 5.0 2.5 4.0 4.5 t h hold time, high or low 3.3 2.0 0 0 ns data to cp 5.0 1.0 1.0 1.0 t w clock pulse width 3.3 3.5 5.5 6.0 ns high or low 5.0 2.5 4.0 4.5 t w mr pulse width 3.3 2.0 5.5 6.0 ns high or low 5.0 1.5 4.0 4.5 t rec recovery time 3.3 1.5 3.5 4.5 ns mr to cp 5.0 1.0 2.0 3.0
5 www.fairchildsemi.com 74ac273 74act273 dc electrical characteristics for act note 8: all outputs loaded; thresholds on input associated with output under test. note 9: maximum test duration 2.0 ms, one output loaded at a time. ac electrical characteristics for act note 10: voltage range 5.0 is 5.0v r 0.5v symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 vi out 50 p a output voltage 5.5 5.49 5.4 5.4 v in v il or v ih 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma (note 8) v ol maximum low level 4.5 0.001 0.1 0.1 vi out 50 p a output voltage 5.5 0.001 0.1 0.1 v in v il or v ih 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 8) i in maximum input 5.5 r 0.1 r 1.0 p av i v cc , gnd leakage current i cct maximum 5.5 0.6 1.5 ma v i v cc 2.1v i cc /input i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 9) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 4.0 40.0 p av in v cc supply current or gnd v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 10) min typ max min max f max maximum clock frequency 2.0 125 189 110 mhz t plh propagation delay 5.0 1.5 6.5 8.5 1.5 9.0 ns t phl cp to q n t phl propagation delay 5.0 1.5 7.0 9.0 1.5 8.5 ns mr to q n
www.fairchildsemi.com 6 74ac273 74act273 ac operating requirements for act note 11: voltage range 5.0 is 5.0v r 0.5v capacitance v cc t a 25 q ct a 40 q c to 85 q c symbol parameter (v) c l 50 pf c l 50 pf units (note 11) typ guaranteed minimum t s setup time, high or low 5.0 1.0 3.5 3.5 ns d n to cp t h hold time, high or low 5.0 0.5 1.5 1.5 ns d n to cp t w clock pulse width 5.0 2.0 4.0 4.0 ns high or low t w mr pulse width 5.0 1.5 4.0 4.0 ns high or low t w recovery time 5.0 0.5 3.0 3.0 ns mr to cp symbol parameter typ units conditions c in input capacitance 4.5 pf v cc open c pd power dissipation capacitance for ac 50.0 pf v cc 5.0v power dissipation capacitance for act 40.0
7 www.fairchildsemi.com 74ac273 74act273 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
www.fairchildsemi.com 8 74ac273 74act273 physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
9 www.fairchildsemi.com 74ac273 74act273 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
www.fairchildsemi.com 10 74ac273 74act273 octal d-type flip-flop physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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